Short-Circuits on FPGAs caused by Partial Runtime Reconfiguration

Transcription

1 2010 International Conerence on Field Prorammable Loic and Applications Short-Circuits on FPGAs caused by Partial Runtime Reconiuration Christian Beckho Dirk Koch and Jim Torresen Department o Inormatics, University o Oslo, Norway {koch, jimtoer}@ii.uio.no Abstract In this paper, we show how short-circuits on FPGAs can be caused by partial runtime reconiuration. Short-circuit can even occur on FPGAs that do not oer any tristate resources just by usin o the shel vendor tools without any bitstream manipulation. The duration o the here presented short-circuits ranes rom short spikes up to persistent short-circuits that remain active durin runtime. Short-circuits will result in increased current consumption and can thus harm the system and must thereore be prevented. An alorithm is derived that detects whether coniuration data will cause short-circuits. We implemented this alorithm in a bitstream scanner that can also be used in systems at runtime. I. INTRODUCTION In typical system on chip desins, multiple modules are connected to a shared bus. On older FPGAs, buses could be implemented with internal tristate buers. Then, modules may only drive their outputs to the bus, i ranted by an arbiter. I the bus is not ranted to the module, the modules output is hih impedance. I the tristate drivers o two modules drive dierent loic values to the bus at the same time, a short-circuit occurs. Such short-circuits result in a current increase that may locally drop the supply voltae levels which may then increase propaation delays, chane sinal states, or heat up the device. Furthermore, the current can be orders o manitude hiher when operatin under shortcircuit conditions. This has thereore stron impact on the reliability o the FPGA that can be aected by eects such as electron miration. Throuhout this paper, we will point out that present FPGA architectures are vulnerable to shortcircuits. To overcome this issue, we present techniques or detectin and preventin short-circuits that can be directly provided by the FPGA-based system itsel. The possibility o connectin multiple drivers to the same wire resource o the FPGA abric was examined in [1]. In that work, the shared column eature o the Altera Flex 8000 amily was used to enerate short-circuits. The shared column eature allows multiple loic cells to drive a shared column interconnect wire resource via pass transistors. In recent FPGAs such as Spartan-3 routin resources are not shared, as sinle driver wires turned to be out more beneicial [2]. Latest FPGAs rom the vendor Xilinx oer tristate buers only or the external I/O pins while the on-chip routin resources are completely unidirectional. Despite the absence o tristate buers, short-circuits in the routin abric o recent Xilinx FPGAs like Spartan-3 still may occur. Here, the multiplexer based implementation o switch matrices allows to connect more than one driver to a wire at the same time. Shortcircuits can lead to unexpected system behavior and oer therewith a possibility to attack systems which use partial runtime reconiuration. This paper will outline the ormat o coniuration data bitstreams in Section II. Next, in Section III, we will reveal inormation about the coniuration data that coniures the switch matrices and show in Section IV how a coniuration can lead to dierent classes o short-circuits. In Section V, we will discuss the impact o short-circuits while Section VI outlines possibilities o preventin short circuits. Section VII will inally conclude this paper. II. CONFIGUATION DATA FORMAT OF VIRTEX-II AND SPARTAN-3 FPGAS The unctionality o FPGAs is controlled by a coniuration bitstream, oranized as a number o consecutive rames. Each rame is one bit wide and coniures parts o the resources available in a column that spans over the ull heiht o an FPGA. Only several rames rouped toether coniure a whole column o e.. coniurable loic blocks, block rams or I/O tiles. For coniuration, irstly a rame is written sequentially into a rame buer reister called rame data input reister. In a second step, the same rame is written rom the rame buer reister into the coniuration SRAM cells o the FPGA abric while concurrently the next rame is written to the rame buer reister. Hence, coniuration is done in a pipelined and consecutive manner. The coniuration memory is oranized in rames as well and rames are the smallest atomic piece o coniuration data that can be written to or read rom coniuration memory. The rame order in bitstreams is outlined in [3] and depicted in Fiure 1. However, detailed inormation e.., on how to coniure a particular routin or loic resource inside a coniurable loic block is omitted in the documentation. In case o Xilinx Virtex-II FPGAs, the irst rames o a bitstream coniure lobal clock resources. These rames are ollowed by rames that coniure the I/O tiles on the very let o the FPGA. Aterwards, the bitstream contains rames that coniure columns o coniurable loic blocks (CLBs), whereas each o these rames contains coniuration data or the I/O tiles on the bottom and top o the FPGA. Ater that, rames or the I/O tiles on the very riht o the FPGA succeed ollowed irstly by rames coniurin the block ram (BRAM) and inally by rames coniurin the BRAM interconnections. The coniuration data or Spartan-3 FPGAs is basically the same but with a dierent number o rames or the particular resources. In this work, rames or coniurable loic blocks are o particular interest. For Virtex-II FPGAs, one column o coniurable loic blocks is coniured by 22 consecutive rames. As illustrated in Fiure 2, each rame starts with twelve bytes coniurin parts o the top I/O tile ollowed /10 $ IEEE DOI /FPL

2 by h 10 bytes o data coniurin parts o each coniurable loic block in the column. Here, h reers to the heiht o the FPGA iven in terms o coniurable loic blocks per column. The rame is closed by aain twelve bytes or coniurin parts o the bottom I/O tile. A column o coniurable loic blocks is completely coniured ater writin 22 rames. A switch matrix o a Virtex-II CLB is based on rouhly 300 coniurable multiplexers that can select rom about 450 dierent inputs. The set o inputs and outputs are not disjoint, i.e., some multiplexer outputs are also connected to the switch matrix as inputs. Each multiplexer is controlled by an exclusive set o coniuration bits and dierent multiplexers do not share the same coniuration bits. The bitstream ormat is identical or each CLB o the FPGA abric and the coniuration data is strictly separated in dedicated data items or each CLB. Respectively, the same holds or the coniuration o block RAMs. While all Virtex-II FPGAs provide an identical switch matrix layout or all devices o the Virtex-II amily, we ound that the available routin resources dier amon the devices o the Spartan-3 amily. The lion s share o the rame data o a CLB coniures the multiplexer settins o the switch matrix and only a small portion o data is used or lookup table unctions and slice internal multiplexer settins [5]. III. SWITCH MATRIX ENCODING For each switch matrix output, a multiplexer controls which input is connected to the output. Settin the select sinals or a multiplexer is achieved by settin the correspondin coniuration bits within one or several rames 1. In depth analysis o bitstreams revealed that two multiplexers never share common coniuration bits and that coniuration bits or one multiplexer miht be spread over several rames. The number o coniuration bits or a particular switch matrix multiplexer varies accordin to its number o inputs. Most 1 These coniuration bits are not documented or present Xilinx FPGAs. However, this inormation has been automatically obtained by eneratin test desins or all switch matrix multiplexers that have been sequentially coniured to all possible input combinations. These permutations are provided by Xilinx via device descriptions in a proprietary lanuae, called Xilinx Desin Lanuae [6]. The resultin bitstreams have been analyzed with the command line tool bitscan, which is included in the ReCoBus-Builder tool suite [7]. As a result, all switch matrix encodins have been enerated and made accessible via an API, which has similarities with JBits [8]. As opposed to JBits, our API can optionally provide detailed inormation about the switch matrix multiplexer encodins within the coniuration bitstream. Global Clock Resource rame Global Clock Resource rame Global Clock Resource rame Global Clock Resource rame 26 rames CLB rame CLB rame CLB rame BRAM rame BRAM rame BRAM Interconnect rame BRAM Interconnect rame n 22 rames 26 rames m 86 rames Fi. 1. Frame order within the coniuration bitstreams o Xilinx Virtex-II FPGAs [3]. The coniuration data or the loic, block RAMs, and the block RAM routin is separated in dedicated sections o the bitstream. CLB y h CLB x IO Tiles Coniurable Loic Block h times 10 bytes h times 10 bytes h times 10 bytes h times 10 bytes 22 rames Fi. 2. Xilinx Virtex-II FPGA example with 25 CLBs surrounded by I/O tiles. The inner columns consist o 22 coniuration rames, while each rame contains 12 + h 10 + o data (see [4] or more details on the structure o Xilinx coniuration bitstreams). h times 10 bytes Fi. 3. A multiplexer with c r = 3 4 = 12 inputs controlled by two 1-hot codes as select sinals. The upper let input is connected to the output. multiplexer settins or Virtex-II FPGAs are coded usin a 2-hot codin scheme (a one 2-code is a binary code with exactly two bits set to one, e ), while only a ew multiplexers use 1-hot or 3-hot codes. For Spartan-3 FPGAs, all multiplexers are coded with 1-hot or 3-hot codes, while only the clock input multiplexers or slices are coded by a 2-hot code. The coniuration bits or a multiplexer with a 2-hot encoded select sinal can be divided into two disjoint roups c and r, so that the 2-hot code results in two 1-hot codes. It is assumed that the switch matrix multiplexers in Xilinx Virtex-II and Spartan-3 FPGAs are implemented with pass transistors that are directly controlled by coniuration SRAM cells. See [9] or more details on the implementation o FPGA switch matrices. A switch matrix multiplexer and the correspondin coniuration memory cells are illustrated in Fiure 3. That multiplexer is coniured by seven coniuration bits m 1 to m 7 that are divided into two disjoint roups c and r. The three coniuration bits in roup c select a particular column, while the our coniuration bits in roup r select a row to connect exactly one column input to the output. Not shown in the iure is a level restorer that keeps the output on a loic 1 -level, i no input is connected. The two roups c and r can be automatically extracted rom the dierent encodins or the multiplexers with the help o raph alorithms. For the ollowin, let us assume a 597

3 input mux coniuration bits (XDL name) index m 1 m 2 m 3 m 4 m 5 m 6 m 5 m 6 NetS6MID NetN2MID NetE6END NetE2END NetS2MID NetS2END NetW6END NetN6MID NetX NetN2END NetY NetN6END NetS6END NetE2END TABLE I EXAMPLE OF THE BITSTREAM ENCODING OF A DOUBLE LINE WITHIN A SPARTAN-3 SWITCH MATRIX. EACH ROW DENOTES A PARTICULAR MULTIPLEXER ENCODING THAT IS SET BY {m 1,..., m 6 }. Fi. 4. a) Coniuration bit raph or the switch matrix multiplexer example in Fiure 3. b) correspondin inverted coniuration bit raph that contains two cliques denotin the coniuration bit roups or controllin the multiplexer. c) Coniuration bit raph or the switch matrix multiplexer example in Fiure 3 assumin that the upper riht input is not used. d) correspondin inverted coniuration bit raph with additional third clique. multiplexer with n inputs that is controlled by m coniuration bits. For each coniuration bit m i a node m i is inserted into an undirected coniuration bit raph. Two dierent nodes m j and m k are adjacent i and only i both coniuration bits m j and m k are equal to one in one o the 2-hot codes. In other words, an ede in the coniuration bit raph corresponds to one particular multiplexer settin. Note that a coniuration bit raph or 2-hot codes is always bipartite with two independent sets o nodes c and r. Let c and r be the number o elements in c and r. I and only i c r = n, the coniuration bit raph is a complete bipartite raph whose inverted raph contains two cliques representin c and r. See Fiure 4 a) and b) or a complete bipartite coniuration bit raph and its inverted raph with two cliques c and r. In case c r > n, then c r n possible inputs remain unused. In this case, additional cliques will be ound in the inverted coniuration bit raph. However, these additional cliques do not correspond to new coniuration bit roups, as the additional cliques contain only nodes that belon also to other cliques, which can be easily identiied. An incomplete coniuration bit raph and the correspondin inverted raph containin an additional third clique is depicted in Fiure 4 c) and d). The here presented alorithm also works or 3-hot codes which are widely used in the encodin o switch matrix multiplexers on Spartan-3 devices. Here, the alorithm commonly detects three cliques which reer to the coniuration bit roups c, r1 and r2. Let us take the switch matrix encodin in Table I o a Spartan double line as a reerence. Then, the correspondin coniuration bit raph and the inverted coniuration bit raph can be derived as illustrated in Fiure 5. As can be Fi. 5. a) Coniuration bit raph or the 3-hot switch matrix multiplexer encodin in Table I. b) correspondin inverted coniuration bit raph that contains three cliques denotin the three coniuration bit roups or the multiplexer (a stand alone node does not match the ormal deinition o a clique in raph theory, but is anyhow here considered as a clique.). seen, there exist three cliques (and consequently three coniuration bit roups), where two cliques contain only one bit. This indicates the use o inverters inside the FPGA to decode these two cliques into the required 1-hot encodins or the two coniuration roups. The inverted coniuration bit raph can be directly translated into a correspondin multiplexer circuit that is depicted in Fiure 6. When considerin the inverted values o the coniuration bits m 5 and m 6, then this results in the two internal coniuration bit roups {m 5, m 5 } and {m 6, m 6 } that are each 1-hot encoded. Note that simple inverters have been ound as the only used variant to decode the state o coniuration SRAM-cells into control sinals or switch matrix pass transistors on Xilinx Spartan-3 FPGAs. In this section, we have summarized properties o the coniuration bitstream encodin and how this properties can be identiied usin coniuration bit raphs. IV. SHORT-CIRCUITS CAUSED BY RECONFIGURATION In this section, we reveal how short-circuits may occur by writin new coniuration data to the FPGA. Short-circuits may harm the sinal interity in other parts o the FPGA by voltae drops or may cause increased power consumption or the overall device as outlined in Section V. This miht lead to unexpected behavior which is extremely diicult to 598

4 Fi. 6. Physical implementation o the 14 input switch matrix multiplexer denoted in Table I. The hihlihted input is connected to the output. Exceptionally, here r1 and r2 are not ormal 1-hot codes but only rom the decodin point o view. The depicted multiplexer implements the codin in Table I. The two struck out inputs are unused, as there are no encodins with {m 1 = 1, m 5 = 0, m 6 = 0} or {m 1 = 1, m 5 = 0, m 6 = 1}. debu. Thereore, short-circuits should be prevented. Shortcircuits can be classiied into three roups accordin to their duration: 1) Lon-term short-circuits can occur any time durin operation o a module and may result rom sinle event upsets or corrupted coniuration data. 2) Medium-term short-circuits can happen when overwritin one coniuration with another one without an intermediate clear step 3) Short-term short-circuits are current spikes in a time rane below a nanosecond. The ollowin three subsections discuss these roups in more detail. A. Lon-Term Short-Circuits There are two possible reasons that may result in a shortcircuit when coniurin a switch matrix multiplexer: 1) at least two hots in c or 2) at least one hot c and at least two bits hot in r. I one o these conditions holds, two multiplexer inputs are connected to the output at the same time. I both o the inputs drive the same loical value, no short-circuit will be caused. Only i the two inputs drive dierent values, a shortcircuit will occur as depicted in Fiure 7. In case o a 1-hot Fi. 7. A multiplexer with an invalid 2-hot code in roup c that causes a short-circuit as the two selected inputs drive each a dierent value. code in roup c and a 2-hot code in roup r a short-circuit may occur as well. Let us start with the assumption that the probability or an input to drive a loical one is p, while the probability to drive a loical zero is 1 p (unused inputs will always drive a loical one and we can hence assume a hiher probability or an input to drive a loical one instead o drivin a loical zero). Let us also assume that the values driven by the dierent inputs are statistically independent. In the event o a k-hot roup c and a l-hot code in roup r, then k l inputs o the multiplexer are connected to the output. No short-circuit will occur, i all the connected inputs drive the same value. The probability p nsc that all inputs drive the same value, either a loical one or a loical zero, and thus no short-circuit occurs is iven in the ollowin equation: p nsc = p k l }{{} + (1 p) k l }{{}. (1) only loical ones only loical zeros I k = l = 1, exactly one input is connected to the output, hence the probability p nsc is equal to one. I not all inputs drive the same value and k l > 1, a short-circuit occurs with the probability p sc = 1 p nsc. Short-circuits caused by erroneous coniuration data will persist durin runtime and are thereore classiied as lon-term short-circuits. B. Medium-Term Short-Circuits Fiure 8 reveals how a medium-term short-circuit is caused by overwritin a coniuration c 1 with c 2. An existin coniuration c 1 in the coniuration memory can be directly overwritten with a new coniuration c 2. As mentioned above, overwritin the existin coniuration c 1 occurs rame wise. Let us assume between the two coniurations c 1 and c 2 the input connected to any iven output o chanes. Then, the 1- hot codes or roup c or roup r or the iven output o also chane. Let us assume that without loss o enerality only the 1- hot code in roup c chanes, while all bits in roup r remain unchaned. Let coniuration bit m j be set in c 1 and coniuration bit m i be set in c 2, with m i, m j c. Further, we assume that coniuration bit m i resides in a rame while m j resides in rame and that rame will be written beore rame. Writin rame o coniuration c 2 to coniuration memory while coniuration c 1 is still active results in a 2-hot code in roup c, as now coniuration bit m i is set to one while coniuration bit m j is also set to one. That may cause a short-circuit as mentioned above. The 2-hot code remains until by writin rame the coniuration bit m j o coniuration c 1 is set back to zero. Short-circuits that remain active between writin two or more dierent rames to coniuration memory are classiied as medium-term short-circuits. Note that the order in which rames are written to coniuration memory is arbitrary. Hence, an inappropriate rame order may increase the expected duration o medium-term short-circuits. But note that reorderin the rame order durin coniuration or omittin a shortcircuit in one multiplexer may cause a short-circuit in another multiplexer that is also coniured by rame and. C. Short-Term Short-Circuits In the above example m i and m j reside in two dierent rames and. Now let us assume that coniuration bit m i and m j reside in the same rame both in coniuration c 1 599

5 a) Two coniurations b) t 1 : Coni. c 1 is active Coni. c 1 Coni. c 2 m i=0 m j=1 m i=1 c) t 2 : Writin rame o coniuration c 2 coniuration memory m i=1 m j=1 invalid 2-hot code m j=0 coniuration memory m i=0 m j=1 valid 1-hot code d) t 3 :Writin rame o coniuration c 2 coniuration memory m i=1 m j=0 valid 1-hot code current consumption [ma] coniuration overwritin writin on blanked area time Fi. 9. Overwritin an existin module coniuration with a new module (coniuration overwritin) causes short-term and medium-term short-circuits that result in increased current consumption as compared to coniurin a blanked reion (writin on blanked area). Fi. 8. a) Coniuration c 1 and c 2 dier both in coniuration bit m i and m j, with m i, m j c. b) At t 1 coniuration c 1 is active. c) At t 2, rame o c 1 is overwritten with rame o c 2. The resultin 2-hot code in c may cause a short-circuit. d) The short-circuit remains active until rame o coniuration c 2 is written to coniuration memory at t 3. and c 2. Althouh within one clock cycle a complete rame is written rom a rame buer reister to coniuration memory, not all bits o coniuration memory will be written at exactly the same time. Let t 1 be the time when coniuration bit m i and the time t 2 when coniuration bit m j is written rom the rame buer reister to coniuration memory. I t 1 < t 2 or the time period δ = t 2 t 1 a 2-hot in c code can cause a shortcircuit. As δ is expected to be very low, these short-circuits are classiied as short-term short-circuits. Note that short-term and medium-term short-circuits may even occur when overwritin an existin coniuration with a coniuration that has a correct checksum and passed the desin rule check by vendor tools. V. IMPACT OF SHORT-CIRCUITS ON POWER CONSUMPTION For determinin the impact o partial reconiuration on the power consumption, a test system has been implemented usin the XUPV2P board rom Diilent. A 100 mω shunt resistor was used to measure the supply current to the board. For the XC2VP30 FPGA o that board, a system was implemented usin ReCoBus-Builder [7] that provides a reconiurable area and a separated static reion that contains the interace loic or the reconiurable modules. Fiure 9 reveals two traces that have been captured when writin the partial coniuration o a video module to the device. One trace illustrates the situation when the module is written on a blanked reion within the reconiurable area while the other trace depicts the case when the video module is overwritin another module that is already located at the taret position o the video module. The heiht o the reconiurable area and the partial module was 67% o the total heiht o the FPGA (in terms o CLBs). Note that the reconiurable area was connected to a separate clock net that was switched o durin reconiuration. Despite the act that the two traces are not only resultin rom the reconiuration process alone but on the total power consumption o the board, a material increase in the power consumption can be identiied when not coniurin on a blanked reconiurable area. Fi. 10. Short-circuit test macro or the hihlihted LUT input multiplexer ( ) within the center CLB. The macro allows to set all inputs o the taret multiplexer to tunable states while additionally allowin to sense chanes to this state by placin dedicated paths that contain one taret input each. For urther investiatin the impact o a short-circuit on the power consumption, dedicated test desins have been implemented usin Xilinx low level tools. This allows in particular to control the directed usae o FPGA resources which is not possible when usin a conventional HDL low. Fiure 10 depicts a macro in the FPGA editor that was used to test the impact o short-circuits in look-up table input multiplexers The current increase depends not only on invalidatin the coniuration bitstream, but also on the state o the inputs that are connected to the switch multiplexers. This state was manually determined or each particular examined resource. The results are summarized in Table II. The maximum extra (static) current that could be drawn via a sinle switch matrix multiplexer was 7.9 ma. This value is by ar beyond normal operation conditions i we have to consider that one CLB has eiht LUTs with our input multiplexers each and that (dependin on the device) an FPGA may posses thousands o CLBs. Consequently, somebody miht think to provide an FPGA virus as a partial module that may draw multiple amperes and that miht potentially permanently damae the device. VI. PREVENTING SHORT-CIRCUITS Medium-term and short-term short-circuits can only occur when an existin coniuration in the coniuration memory 600

6 resource # con. bits # Mux inputs extra current LUT input ma Double line ma Clock input ma TABLE II MAXIMUM CURRENT INCREASE FOUND ON A SPARTAN-3 FPGA WHEN INVALIDATING A SINGLE SWITCH MATRIX MULTIPLEXER. is overwritten, e.. when a new module shall be coniured to a module slot that contains a module already. In order to prevent short-circuits, beore coniurin the new module, the user has to coniure the module slot such that it only contains the communication inrastructure that connects the module with the static part but not any other loic or routin. This coniuration scheme can be enorced by a coniuration driver that rejects write accesses to any unblanked coniuration memory reion. Partially reconiurable systems based on the ReCoBus communication inrastructure can be desined or open system use, so that third party developers provide a module as a bitstream that the user can link into the already existin system [7]. These third party modules could (intentionally, in case o a virus) cause lon-term short-circuits. This can be detected as described in the ollowin. A. A bitstream scanner or detectin possible short-circuits Currently, the ReCoBus-Builder tool chain provides a sotware implementation o a bitstream scanner that can detect lon-term short-circuits. This is possible by testin or each switch matrix multiplexer i the correspondin coniuration is valid or not. In addition, the bitstream scanner can veriy i the third party module contains the required ReCoBus communication inrastructure. Note that it is impossible to prevent short-term and medium-term short-circuits at synthesis, as the later context o the bitstream in the partial system is unknown. A hardware implementation o the bitstream scanner would have to keep track or both roups r and c o all multiplexers i within a roup there is a hot bit already. I an erroneous rame contains a second hot bit or any roup, the bitstream scanner would rejected the rame. Note that scannin or short circuits in 3-hot coded multiplexers like the one depicted in Fiure 5, the scanner has only to keep track whether in roup c there is more than one bit set. This would siniicantly reduce the hardware overhead. Note that coniuration data can also be chaned by sinle event upsets, both in the coniuration memory and in an ochip memory that is used or storin coniuration data. In the second case, a bitstream scanner could detect erroneous coniuration data. In both cases, checksum sel-test o coniuration data would not help to prevent short-circuits as the CRC violation is only detected ater writin the coniuration. Note that it is trivial to manipulate a coniuration bitstream that will still pass the built-in CRC check, hence CRC checks can not detect viruses. Short-circuits in FPGAs can also be used to attack a system. Three levels o system attacks are iven in [1]: While Level 0 attacks use short-circuits to produce instability, Level 1 attacks violate a bus protocols and Level 2 obey the bus protocol and use valid bus transactions to trier harmul system tasks. The classiication o short-circuits accordin to their duration in this paper stands orthoonal to Level 0 attacks in [1]. Note that our bitstream scanner can be used to prevent Level 0 attacks. However Level, 1 and Level 2 attacks can only be detected by source code analysis or by simulation. To orce the placer and the router to implement a module in a iven area, Xilinx provides so called area constraints. However, the area constraints in current Xilinx releases contain a limitation. While the placer obeys the area constraints, the router will violate the area constraints as the loic utilization rows (this even holds when usin the Xilinx PR-Patch [10]). Routin paths rom neihborin module slots that cross the module boundary complicate blankin a module slot, as theses routin paths may not be interrupted durin blankin. Blocker macros that are part o the ReCoBus-Builder tool chain prevent routin violation and thereore acilitate blankin a module slot. VII. CONCLUSION In this paper we showed how short-circuits can be caused by coniuration at runtime. Short-circuits can be classiied accordin to their duration and lead to and increased current consumption. However, the ReCoBus-Builder tool chain oers a sotware implementation o a bitstream scanner, that detects short-circuits. In uture work, we will present a hardware implementation o a bitstream scanner and examine shortcircuits on newer FPGAs. ACKNOWLEDGMENT This work is supported in part by the Norweian Research Council under rant V30 REFERENCES [1] Ilija Hadzic and Sanjay Udani and Jonathan M. Smith, FPGA Viruses, in FPL, 1999, pp [2] G. Lemieux, E. Lee, M. Tom, and A. Yu, Directional and Sinle- Driver Wires in FPGA Interconnect, in IEEE International Conerence on Field-Prorammable Technoloy (FPT), [3] Xilinx Inc., Virtex-II Pro and Virtex-II Pro X FPGA User Guide, November [4] Dirk Koch, Architectures, Methods and Tools or Distributed Run-time Reconiurable FPGA-based Systems, Ph.D. dissertation, University o Erlanen-Nurember, [5] A. Sinh and M. Marek-Sadowska, FPGA Interconnect Plannin, in SLIP 02: Proceedins o the 2002 International Workshop On System- Level Interconnect Prediction. New York, NY, USA: ACM, 2002, pp [6] Xilinx Inc., The Xilinx Desin Lanuae, July [7] D. Koch, C. Beckho, and J. Teich, ReCoBus-Builder a Novel Tool and Technique to Build Statically and Dynamically Reconiurable Systems or FPGAs, in Proceedins o International Conerence on Field-Prorammable Loic and Applications (FPL 08), Heidelber, Germany, Sep. 2008, pp [8] Xilinx Inc., JBits 3.0 SDK or Virtex-II. [9] D. Lewis, E. Ahmed, G. Baeckler, V. Betz, M. Boureault, D. Cashman, D. Galloway, M. Hutton, C. Lane, A. Lee, P. Leventis, S. Marquardt, C. McClintock, K. Padalia, B. Pedersen, G. Powell, B. Ratchev, S. Reddy, J. Schleicher, K. Stevens, R. Yuan, R. Cli, and J. Rose, The Stratix II loic and routin architecture, in FPGA 05: Proceedins o the 2005 ACM/SIGDA 13th international symposium on Fieldprorammable ate arrays. New York, NY, USA: ACM, 2005, pp [10] Xilinx Inc., Partial Reconiuration User Guide, March