Accelerating Design Space Exploration Using Pareto-Front Arithmetics

Transcription

1 Session 6A-1: Accelerating Design Sace Exloration Using Pareto-Front Arithmetics Christian Haubelt, Jürgen Teich University of Paderborn Paderborn, Germany {haubelt, University of Paderborn ASPDAC 03 Kitakyushu Deartment of Electrical Engineering and Information Technology Institute DATE Prof. Dr.-Ing. Jürgen Teich

2 Outline System synthesis Hierarchical system synthesis Hierarchical design sace Hierarchical objective sace Hierarchical design sace exloration Pareto-Front Arithmetics (PFA) PFA with uncertain objectives Results Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 2

3 Introduction Problems in system synthesis: Tyical design saces consist > design oints Task of system synthesis is NP-comlete Solutions: wait for the results... Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 3

4 Introduction Problems in system synthesis: Tyical design saces consist > design oints Task of system synthesis is NP-comlete Solutions: wait for the results... Use efficient search strategies: Hierarchical roblem descrition Otimizing subsystems Combining results at higher levels of hierarchy Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 3

5 Outline System synthesis Hierarchical system synthesis Hierarchical design sace Hierarchical objective sace Hierarchical design sace exloration Pareto-Front Arithmetics (PFA) PFA with uncertain objectives Results Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 4

6 Secification of an MPEG4 Coder C 1 DL C 2 CL C 3 AL C 4 FL C 5 Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 5

7 Secification of an MPEG4 Coder C 1 DL C 2 CL C 3 AL C 4 FL C 5 Network FPGA2 RISC1 Scene SB FPGA1 RISC2 Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 5

8 Secification of an MPEG4 Coder C 1 DL C 2 CL C 3 AL C 4 FL C 5 Network FPGA2 RISC1 Scene SB FPGA1 RISC2 Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 5

9 Secification of an MPEG4 Coder C 1 DL C 2 CL C 3 AL C 4 FL C 5 = 0 =100 =10 = 200 =10 =300 =0 =100 = 0 = 400 FPGA2 =700 c=500 = 350 SB =50 c=50 SB RISC1 =450 c=750 Network =0 c=0 Scene =0 c=0 FPGA1 =600 c=1000 RISC2 =400 c=800 Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 5

10 Imlementation C 1 DL C 2 CL C 3 AL C 4 FL C 5 = 0 =100 =10 = 200 =10 =300 =0 =100 = 0 SB =50 c=50 SB RISC1 =450 c=750 Network =0 c=0 Scene =0 c=0 RISC2 =400 c=800 Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 6

11 System Synthesis Imlementation (α, β) Otimization: minimize o(α, β), subject to: α is a feasible allocation, β is a feasible binding, c i (α, β) 0, i {1,..., q}. Design sace X = {(α, β)} Feasible set X f = {(α, β) (α, β) is feasible} X Objective sace Y f = o(x f ) Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 7

12 Pareto-Otimality Pareto set X X Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 8

13 Pareto-Otimality Pareto set X X Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 8

14 Pareto-Otimality Pareto set X X Quality set X q Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 8

15 Objective Sace Imlementation cost: sum of all cost of the resources in the allocation Power consumtion: sum of all ower consumtion of the resources in the allocation + sum of all additional ower consumtion resulting from the binding Flexibility: number of imlemented leaf grahs Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 9

16 Results C % t Non Hierarchical Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 10

17 Outline System synthesis Hierarchical system synthesis Hierarchical design sace Hierarchical objective sace Hierarchical design sace exloration Pareto-Front Arithmetics (PFA) PFA with uncertain objectives Results Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 11

18 Hierarchical Secification of Embedded Systems v 1 g 1 r 2 v 2 g 2 r 1 g g a Θ(g s, g ) = (g s, g 1 ) (g s, g 2 ) Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 12

19 Hierarchical Design Sace (1/2) Problem 1: tyical design sace consists of many infeasible solutions Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 13

20 Hierarchical Design Sace (1/2) Problem 1: tyical design saces consist of many infeasible solutions Advantages of hierarchical design sace exloration: 1. each artial secification to-level secification 2. smaller comlexity of each subsystem 3. valid to-level design may only be comosed of valid subsystem designs number of evaluated designs is a small fraction of the original search sace Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 13

21 Hierarchical Design Sace (2/2) Problem 2: Pareto-otimal to-level design comosed of Paretootimal subsystems iff all objective functions are monotonic Imlementation cost: sum of all cost of the resources in the allocation Power consumtion: sum of all ower consumtion of the resources in the allocation + sum of all additional ower consumtion resulting from the binding Flexibility: number of imlemented leaf grahs Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 14

22 Hierarchical Design Sace (2/2) Problem 2: Pareto-otimal to-level design comosed of Paretootimal subsystems iff all objective functions are monotonic Imlementation cost: sum of all cost of the resources in the allocation Power consumtion: sum of all ower consumtion of the resources in the allocation + sum of all additional ower consumtion resulting from the binding Flexibility: number of imlemented leaf grahs Most objectives in system design are non-monotonic! Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 14

23 Non-Monotonic Objective Saces v 1 g 1 r 2 c=100 v 2 g 2 r 1 c=200 g g a cost(x (g s, g 1 )) = {(100)} cost(x (g s, g 2 )) = {(200)} cost(x (g s, g )) = {(200)} = {(300)} Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 15

24 Outline System synthesis Hierarchical system synthesis Hierarchical design sace Hierarchical objective sace Hierarchical design sace exloration Pareto-Front Arithmetics (PFA) PFA with uncertain objectives Results Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 16

25 PFA Oeration: Union Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 17

26 PFA Oeration: Union Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 17

27 PFA Oeration: Maximum Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 18

28 PFA Oeration: Maximum Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 18

29 PFA Oeration: Addition Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 19

30 PFA Oeration: Addition Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 19

31 Results C % (), t Non Hierarchical PFA Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 20

32 PFA with Uncertain Objectives Addition Maximum Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 21

33 PFA with Uncertain Objectives Addition Maximum Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 21

34 Uncertain Dominance a e b e? b c d Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 22

35 Uncertain Dominance a e b e? Yes! a e? b c d Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 22

36 Uncertain Dominance a e b e? Yes! a e? Probably yes. b c d P [a b] = m i=1 P [o i (a) o i (b)], Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 22

37 Outline System synthesis Hierarchical system synthesis Hierarchical design sace Hierarchical objective sace Hierarchical design sace exloration Pareto-Front Arithmetics (PFA) PFA with uncertain objectives Results Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 23

38 UT b Results C % 86% t Non Hierarchical PFA PFI, 33% PFI, 45% Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 24

39 UT b Results C 9 h h 4 h min 23 h t Non Hierarchical PFA PFI, 33% PFI, 45% Christian Haubelt Accelerating Design Sace Exloration ASPDAC 03 24