Page CPU, Reset, oscillators, jtag/swd/trace connectors Page Ethernet interface Page SPI-FLASH and IC-EPROM Page jtag/swd/trace connectors Reset generator xleds 0/00Mbps Ethernet PHY LAN0 (RMII I/F) MHz crystal.khz crystal LPC MCU SPI-bus All other mcu pins x SDRAM (when x databus) x SDRAM (when x databus) Memory bus (dynamic and static) SPI-NOR flash (optional) IC-bus IC-EPROMs Config info Memory bus buffers NAND flash (usd interface as alternative) Memory bus (static) SDRAM 00pos edge connector, V key Page External bus buffers Page NAND flash Page LEDs and configuration IC-EPROM Rev A First revision Page 9 SODIMM edge connector = UnLoaded = normally not mounted component. Default jumper settings are indicated in the schematic. However, always check jumper positions on actual boards since there is no guarantee that all jumpers are in default place.
MHz pf pf pf pf.khz BLMAG0S BLMAG0S RED K MIC-9DUY 0uF 0uF 0uF 0uF LPC LPC LPC LPC LPC LPC C C C C C9 C C C C C Y C C C C9 C C C C D D C C Y L L LED R R MR# RESET# U C0 R0 R R R R9 R C R R R R R R0 R X 9 0 9 0 X 9 0 R R R R R R9 TP C0 C C C C C UG$ P0.0/CAN_RD/U_TXD/IC_SDA/U0_TXD U P0./CAN_TD/U_RXD/IC_SCL/U0_RXD T P0./U0_TXD/U_TXD C P0./U0_RXD/U_RXD D P0./IS_RX_SCK/CAN_RD/T_CAP0/LCD_VD0 B P0./IS_RX_WS/CAN_TD/T_CAP/LCD_VD C P0./IS_RX_SDA/SSP_SSEL/T_MAT0/U_RTS/LCD_VD D P0./IS_TX_CLK/SSP_SCK/T_MAT/LCD_VD9 C P0./IS_TX_WS/SSP_MISO/T_MAT/LCD_VD A P0.9/IS_TX_SDA/SSP_MOSI/T_MAT/LCD_VD C P0.0/U_TXD/IC_SDA/T_MAT0 T P0./U_RXD/IC_SCL/T_MAT R P0./USB_PPWR/SSP_MISO/ADC0_IN R P0./USB_UP_LED/SSP_MOSI/ADC0_IN R P0./USB_HSTEN/SSP_SSEL/USB_CONNECT T P0./U_TXD/SSP0_SCK J P0./U_RXD/SSP0_SSEL J P0./U_CTS/SSP0_MISO K P0./U_DCD/SSP0_MOSI K P0.9/U_DSR/SD_CLK/IC_SDA L P0.0/U_DTR/SD_CMD/IC_SCL M P0./U_RI/SP_PWR/U_OE/CAN_RD M P0./U_RTS/SD_DAT0/U_TXD/CAN_TD N P0./ADC0_IN0/IS_RX_CLK/T_CAP0 H P0./ADC0_IN/IS_RX_WS/T_CAP G P0./ADC0_IN/IS_RX_SDA/U_TXD F P0./ADC0_IN/DAC_OUT/U_RXD E P0./IC0_SDA/USB_SDA T P0./IC0_SCL/USB_SCL R P0.9/USB_D+/EINT_0 U P0.0/USB_D-/EINT_ R P0./USB_D+ T USB_D- U UG$ P.0/ENET_TXD0/T_CAP/SSP_SCK A P./ENET_TXD/T_MAT/SSP_MOSI B P./ENET_TXD/SD_CLK/PWM0_ D9 P./ENET_TXD/SD_CMD/PWM0_ A0 P./ENET_TX_EN/T_MAT/SSP_MISO A P./ENET_TX_ER/SD_PWR/PWM0_ A P./ENET_TX_CLK/SD_DAT0/PWM0_ B P./ENET_COL/SD_DAT/PWM0_ D P./ENET_CRS/T_MAT/SSP_SSEL C P.9/ENET_RXD0/T_MAT0 A P.0/ENET_RXD/T_CAP0 C P./ENET_RXD/SD_DAT/PWM0_ A P./ENET_RXD/SD_DAT/PWM0_CAP0 A P./ENET_RX_DV D P./ENET_RX_ER/T_CAP0 A P./ENET_RX_CLK/IC_SDA A P./ENET_MDC/IS_TX_MCLK D0 P./ENET_MDIO/IS_RX_MCLK A9 P./USB_UP_LED/PWM_/T_CAP0/SSP_MISO P P.9/USB_TX_E/USB_PPWR/T_CAP/MC_0A/SSP_SCK/U_OE U P.0/USB_TX_DP/PWM_/QEI_PHA/MC_FB0/SSP0_SCK/LCD_VD/LCD_VD0 U P./USB_TX_DM/PWM_/SSP0_SSEL/MC_ABORT/LCD_VD/LCD_VD R P./USB_RCV/USB_PWRD/T_MAT0/MC_0B/SSP_MOSI/LCD_VD/LCD_VD U P./USB_RX_DP/PWM_/QEI_PHB/MC_FB/SSP0_MISO/LCD_VD9/LCD_VD P9 P./USB_RX_DM/PWM_/QEI_IDX/MC_FB/SSP0_MOSI/LCD_VD0/LCD_VD T9 P./USB_LS/USB_HSTEN/T_MAT/MC_A/CLKOUT/LCD_VD/LCD_VD T0 P./USB_SSPND/PWM_/T0_CAP0/MC_B/SSP_SSEL/LCD_VD/LCD_VD0 R0 P./USB_INT/USB_OVRCR/T0_CAP/CLKOUT/LCD_VD/LCD_VD T P./USB_SCL/PWM_CAP0/T0_MAT0/MC_A/SSP0_SSEL/LCD_VD/LCD_VD T P.9/USB_SDA/PWM_CAP/T0_MAT/MC_B/U_TXD/LCD_VD/LCD_VD U P.0/USB_PWRD/USB_VBUS/ADC0_IN/IC0_SDA/U_OE P P./USB_OVRCR/SSP_SCK/ADC0_IN(IC0_SCL P UG$ P.0/PWM_/U_TXD/LCD_PWR B P./PWM_/U_RXD/LCD_LE E P./PWM_/U_CTS/T_MAT/TRACEDATA/LCD_DCLK D P./PWM_/U_DCD/T_MAP/TRACEDATA/LCD_FP E P./PWM_/U_DSR/T_MAT/TRACEDATA/LCD_ENAB_M D P./PWM_/U_DTR/T_MAT0/TRACEDATA0/LCD_LP F P./PWM_CAP0/U_RI/T_CAP0/U_OE/TRACECLK/LCD_VD0/LCD_VD E P./CAN_RD/U_RTS/LCD_VD/LCD_VD G P./CAN_TD/U_TXD/U_CTS/ENET_MDC/LCD_VD/LCD_VD H P.9/USB_CONNECT/U_RXD/U_RXD/ENET_MDIO/LCD_VD/LCD_VD H P.0/EINT0/NMI N P./EINT/SD_DAT/IS_TX_CLK/LCD_CLKIN T P./EINT/SD_DAT/IS_TX_WS/LCD_VD/// N P./EINT/SD_DAT/IS_TX_SDA/LCD_VD/9/9 T P./EMC_CS/IC_SDA/T_CAP0 R P./EMC_CS/IC_SCL/T_CAP P P./EMC_CAS R P./EMC_RAS R P./EMC_CLK0 U P.9/EMC_CLK R P.0/EMC_DYCS0 T P./EMC_DYCS U P./EMC_DYCS/SSP0_SCK/T_CAP0 U P./EMC_DYCS/SSP0_SSEL/T_CAP U P./EMC_CKE0 P P./EMC_CKE R P./EMC_CKE/SSP0_MISO/T_MAT0 T P./EMC_CKE/SSP0_MOSI/T_MAT P P./EMC_DQM0 P P.9/EMC_DQM N P.0/EMC_DQM/IC_SDA/T_MAT L P./EMC_DQM/IC_SCL/T_MAT N UG$ P./EMC_D/T_MAT J P.0/EMC_D0/U_RTS/T_MAT H P.9/EMC_D9/PWM_/T_MAT0 F P./EMC_D/PWM_/T_CAP D P./EMC_D/PWM_/T_CAP0 A P./EMC_D/PWM_/T0_MAT/STCLK T P./EMC_D/PWM_/T0_MAT0 U P./EMC_D/PWM_/T0_CAP R P./EMC_D/PWM_CAP0/T0_CAP0 T P./EMC_D/PWM0_CAP0/U_RI C P./EMC_D/PWM0_/U_DTR C0 P.0/EMC_D0/PWM0_/U_DSR A P.9/EMC_D9/PWM0_/U_DCD B P./EMC_D/PWM0_/U_CTS C P./EMC_D/PWM0_/U_RXD F P./EMC_D/PWM0_/U_TXD F P./EMC_D M P./EMC_D H P./EMC_D C P./EMC_D D P./EMC_D D P.0/EMC_D0 B P.9/EMC_D9 C P./EMC_D D P./EMC_D L P./EMC_D J P./EMC_D G P./EMC_D F P./EMC_D E P./EMC_D B P./EMC_D B P.0/EMC_D0 B UG$ P./EMC_CS A P.0/EMC_CS0 B P.9/EMC_BLS/U_RXD/T_MAT/IC_SCL/LCD_VD// B0 P./EMC_BLS/U_TXD/T_MAT0/LCD_VD/0/ C P./EMC_BLS G P./EMC_BLS0 L P./EMC_WE B9 P./EMC_OE B P./EMC_A/U_RXD/SSP_MOSI J P./EMC_A/U_TXD/SSP_MISO K P./EMC_A/IC_SCL/SSP_SSEL M P.0/EMC_A0/IC_SDA/SSP_SCK R P.9/EMC_A9 P P./EMC_A P P./EMC_A P P./EMC_A U P./EMC_A A P./EMC_A B P./EMC_A B P./EMC_A C P./EMC_A F P.0/EMC_A0 G P.9/EMC_A9 H P./EMC_A J P./EMC_A L P./EMC_A M P./EMC_A R P./EMC_A R P./EMC_A U P./EMC_A T P./EMC_A U0 P.0/EMC_A0 U9 UG$ JTAG_TDO_SWO D JTAG_TDI C JTAG_TMS_SWDIO E JTAG_TRST D P./U0_OE/T_MAT/U_TXD C JTAG_TCK_SWDCLK E RSTOUT K P./U_RXD/IC0_SCL G RESET M RTC_ALARM N X N X M RTCX L RTCX K L T R9 P N H E A B A -REG D -REG K A J -REG P0 P P U P K C B C9 D -REGV H -REGV P -REGV D P.0/EMC_A/T_MAT F P./EMC_A/T_MAT J P./T_MAT/IC0_SDA L VREFP K A G VBAT M G RESET_IN RESET_IN RESET_IN P0.-SDA0 P0.-SCL0 VREF VBAT_IN VA A VBAT P0. P0. P0. P0. P0. P0.-USB_D+ USB_D- P0. P0. P0. P0. P0.0 P0. P0. P0. P0.9 P0.0 P0. P0. P0.-SSP0_SCK P0.-SSP0_SSEL P0.-SSP0_MISO P0.-SSP0_MOSI P0. P0. P0. P0.9 P0.0 P0. P.0-RMII_TXD0 P.-RMII_TXD P.-RMII_TXEN P.9-RMII_RXD0 P.0-RMII_RXD P.-RMII_RXER P.-RMII_MCD P.-RMII_MDIO P.-MCICLK P.-MCICMD P.-MCIPWR P.-MCIDAT0 P.-MCIDAT P.-MCIDAT P.-MCIDAT P.-RMII_CLK P.-RMII_CRS P. P. P.0 P. P. P. P. P. P. P. P.0 P.9 P.0 P.-CAS P.-RAS P.-CS P.0-DYCS0 P. P.-CLKOUT0 P.9 P.-CKE0 P. P.-DQM0 P.9-DQM P.-CS P. P. P.0-DQM P.-DQM P. P. P.9 P. P.-TRACEDATA P.-TRACEDATA P.-TRACEDATA P.-TRACEDATA P.-TRACEDATA0 P.-TRACEDATA0 P. P. P.0 P.-TRACEDATA P.-TRACEDATA P. P. P. P.0-CS0 P.-CS P.0-A0 P.-A P.-A P.-A P.-A P.-A P.-A P.-A P.-A P.9-A9 P.0-A0 P.-A P.-A P.-A P.-A P.-A P.-A P.-A P.-A P.9-A9 P.0-A0 P.-A P.-OE P.-WE P.-BLS0 P.-BLS P.-BLS P.9-BLS P.-A P.-A P.-D P.-D P.0-D0 P.-D P.-D P.-D P.-D P.-D P.-D P.-D P.-D P.9-D9 P.0-D0 P.-D P.-D P.-D P.-D P.-D P.-D P.-D P.-D P.9-D9 P.0-D0 P.-D P.-D P.0-D0 P.-D P.-D P.-D P.-D P.-D P.9-D9 TCK_SWDCLK TCK_SWDCLK JTAG_TRST TMS_SWDIO TMS_SWDIO TDI TDI TDO_SWO TDO_SWO RTC_ALARM RESET_OUT P. P. P.9 P0.9-USB_D+ P0.0-USB_D- P.-TRACECLK P.-TRACECLK P.0 P. P. P. P. P. Place at U, pin G, P, P, U, P, K, C, B, C9, D, H, P, D Reset generation SWD/JTAG and Trace interface LPC MCU.9V threshold (or STMSDWF) X and X not mounted
00/0M Ethernet PHY (via RMII interface) L BK0HS0-T or BLMPGSND (A 0mohm) C9 0uF C0 C C C 0uF C C To RJ Ethernet connector P.0-RMII_TXD0 P.-RMII_TXD P.-RMII_TXEN P.9-RMII_RXD0 P.0-RMII_RXD P.-RMII_CRS P.-RMII_RXER P.-RMII_MDIO P.-RMII_MCD RESET_OUT P.-RMII_CLK R R9 R0 R R R R R R R UG$ LVCG0GW R9 R K R 0K R 0K U LAN0 TXD0 TXD TXEN RXD0/MODE0 RXD/MODE CRS_DV/MODE 0 RXER/PHYAD0 MDIO MDC NINT/REFCLKO NRST LED/REGOFF LED/NINTSEL Y MHz TP A 9 A IO 9 CR XTAL/CLKIN XTAL RBIAS R K, % uf TXP ETH_TXP TXN 0 ETH_TXN RXP ETH_RXP RXN ETH_RXN R R R R _A ETH_TXP ETH_TXN ETH_RXP ETH_RXN C C C C9 External LEDs active low UG$ C R0 C0 M pf C pf R Q BSS R Q BSS ETH_LED ETH_LED 00M or 0M RX/TX activity
Serial memories (IC-EPROM / SPI-FLASH) Mbit SPI-NOR Flash (normally not mounted) kbit EEPROM P0.-SSP0_SSEL P0.-SSP0_MOSI P0.-SSP0_MISO P0.-SSP0_SCK RESET_OUT SJ R - normally shorted U SSTVF0 or MXL0EMI-G CS SI SO C C SCK WP HOLD P0.-SDA0 P0.-SCL0 R K R K U LC SDA SCL A A A0 EEPROM Array WP C U ATDBD-SU SI SO RESET# SCK WP# CS# IC address:.0..0.0.0.0.rw U and U on overlapping pads (cannot be mounted simultaneous)
Mbit (MByte) SDRAM (DYCS0 = 0xA000 0000-0xAFFF FFFF) SDRAM -bit databus version -bit databus version C P.0-A0 P.-A P.-A P.-A P.-A P.-A P.-A P.-A P.-A P.9-A9 P.0-A0 P.-A P.-A P.-A P.-A P.9-DQM P.-DQM0 P.-CLKOUT0 P.-CKE0 P.0-DYCS0 P.-RAS P.-CAS P.-WE C C U9 KSH or MTLCM A0 DQ0 D0 A DQ D A DQ D A DQ D 9 A DQ D 0 A DQ 0 D A DQ D A DQ D A DQ D A9 DQ9 D9 A0/AP DQ0 D0 A DQ D A DQ D DQ 0 D 0 BA0 DQ D BA DQ D 9 9 0 DQM LDQM CLK CKE CS RAS CAS WE NC Q Q 9 Q Q 9 Q Q Q Q C9 C0 C C C RNA RNB RNC RND RNA RNB RNC RND RNA RNB RNC RND RNA RNB RNC RND P.0-D0 P.-D P.-D P.-D P.-D P.-D P.-D P.-D P.-D P.9-D9 P.0-D0 P.-D P.-D P.-D P.-D P.-D C 0uF P.0-A0 G P.-A G9 P.-A F P.-A F P.-A G P.-A G P.-A G P.-A H P.-A H P.9-A9 J P.0-A0 G P.-A H9 P.-A H P.-A J P.-A H P.-RAS J9 P.-CAS K P.-WE K P.-CLKOUT0 J P.-CKE0 J P.0-DYCS0 J P.-DQM0 K9 P.9-DQM K P.0-DQM F P.-DQM F A F L R B B C D E9 L9 M N P P U0 KMG-HN A0 D0 A D A D A D A D A D A D A D A D A9 D9 A0 D0 A D (A) D BA0 D BA D RAS_N D CAS_N D WE_N D CLK D CKE D9 CS_N D0 DQM0 D DQM D DQM D DQM D D D D D D9 D0 D Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q R N R9 N P9 M M L L M M P N R N R E D D B9 C A9 C A A C A C B D D E A F9 L R B B C9 D9 E L M9 N9 P P D0 D D D D D D D D D9 D0 D D D D D RNA RNB RNC RND RNA RNB RNC RND RNA RNB RNC RND RNA RNB RNC RND P.-D P.-D P.-D P.9-D9 P.0-D0 P.-D P.-D P.-D P.-D P.-D P.-D P.-D P.-D P.9-D9 P.0-D0 P.-D P.0-DYCS0 P.-RAS P.-CAS P.-CKE0 P.-DQM0 P.9-DQM R9 R0 R R R R C C00 C C0 C C C9 C0 C C9 C9 C9 C9 C99 C 0uF P.0-DQM P.-DQM R R
Address and Control Buffers P.-A P.-A U LVCGDC A Y A Y OE OE BA BA C Buffers for external memory bus Databus Buffers Pullups Buffered bus for static memories: CS0 = 0x000 0000-0xFF FFFF CS = 0x9000 0000-0x9FF FFFF CS = 0x900 0000-0x9BFF FFFF CS = 0x9C00 0000-0x9FFF FFFF P.-A P.-A P.-A P.9-A9 P.0-A0 P.-A P.-OE P.-WE P.-BLS0 P.-BLS P.-BLS P.9-BLS P.0-CS0 P.-CS P.-CS P.-CS 0 0 9 UG$ SNLVC or SNAVCA A B BA A B BA A B BA A B BA9 A B BA0 A B 9 BA A B BOE A B BWE A B BBLS0 A B BBLS A B BBLS A B BBLS A B 9 BCS0 A B 0 BCS A B BCS A B BCS G DIR G DIR P.-D P.-D P.-D P.-D P.-D P.0-D0 P.9-D9 P.-D P.-D P.-D P.-D P.-D P.-D P.-D P.-D P.0-D0 BBLS BOE BBLS0 R9 R R 0 0 9 UG$ SNLVC or SNAVCA A B BD A B BD A B BD A B BD A B BD A B 9 BD0 A B BD9 A B BD A B BD A B BD A B BD A B BD A B 9 BD A B 0 BD A B BD A B BD0 G DIR G DIR P.-CS P.-CS P.-CS P.0-CS0 P.9-BLS P.-BLS P.-BLS P.-BLS0 P.-WE P.-OE P.-D P.-D R R R R R9 R0 R R R R R R0 Boot control (not used) SJ P.-A P.-A P.-A P.-A P.-A P.0-A0 P.9-A9 P.-A P.-A P.-A P.-A P.-A P.-A P.-A P.-A P.0-A0 ABUF_EN - normally shorted UG$ SNLVC or SNAVCA A B BA A B BA A B BA A B BA A B BA 0 A B 9 BA0 A B BA9 A B BA A B BA A B BA A B BA A B BA 0 A B 9 BA 9 A B 0 BA A B BA A B BA0 G DIR G DIR P.-D P.-D P.-D P.9-D9 P.0-D0 P.-D P.-D P.-D P.-D P.-D P.-D P.-D P.-D P.9-D9 P.0-D0 P.-D BBLS R BBLS R 0 0 9 UG$ SNLVC or SNAVCA A B BD A B BD A B BD A B BD9 A B BD0 A B 9 BD A B BD A B BD A B BD A B BD A B BD A B BD A B 9 BD A B 0 BD9 A B BD0 A B BD G DIR G DIR -bit databus version (P. - P. are buffered) -bit databus version (P. - P. are not buffered) P.-D P.0-D0 P.9-D9 P.-D P.-D P.-D P.-D P.-D P.-D P.-D P.-D P.0-D0 P.9-D9 P.-D P.-D P.-D RND RNC RNB RNA RND RNC RNB RNA RN0D RN0C RN0B RN0A RN9D RN9C RN9B RN9A BD BD0 BD9 BD BD BD BD BD BD BD BD BD0 BD9 BD BD BD UG$ 0 9 C C C C UG$ 0 9 C C9 C0 0uF C C C 0uF _EXT C C UG$ C C C C9 C0 UG$ C C C C C C 0uF 0uF 0uF 0uF 0uF 0 9 0 9
NAND Flash memory (on buffered bus) Gbit (MByte) NAND FLASH (CS = 0x9000 0000-0x9FF FFFF) _EXT BCS R90 BD0 BD BD BD BD BD BD BD BA0 BA9 BOE BWE R 0K R9 NAND_FLASH_RDY 0K U K9FG0U0C-P 9 IO0 0 IO IO IO IO IO IO IO CLE ALE 9 CE_N RE_N WE_N 9 WP_N R/B_N C C C9 0uF U and X on overlapping pads (cannot be mounted simultaneous) usd/transflash Memory Card I/F (normally not mounted) Q FDNP R9 0K R9 0K R9 0K R9 0K R9 0K R9 0K R9 K R9 K C90 C9 0uF R99 0K P.-MCIPWR LED RED P.-MCIDAT P.-MCIDAT P.-MCICMD P.-MCICLK P0. P.-MCIDAT0 P.-MCIDAT R00 R0 R0 R0 R0 R0 R0 0 0 0 0 0 0 P0. R0 CARD_DETECT TP CD NC- NC- X 0009 DAT DAT/CD CMD CLK DAT0 DAT CD NC NC
Configuration IC-EPROM and LEDs kbit Configuration EEPROM (write protected) LEDs P0.-SDA0 P0.-SCL0 U LC SDA SCL A A A0 IC address:.0..0..0..rw EEPROM Array WP 0K C9 P. P. UG$ LVCGGW U9G$ LVCGGW R0 LED K RED R09 LED K GREEN R0 TP TP SJ - normally shorted TP TP U9G$ UG$
0-SLOT_.V 0uF 0uF R R R R X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-90 X-9 X-9 X-9 X-9 X-9 X-9 X-9 X-9 X-99 X-00 X-0 X-0 X-0 X-0 X-0 X-0 X-0 X-0 X-09 X-0 X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-0 X- X- X- X- X- X- X- X- X-9 X-90 X-9 X-9 X-9 X-9 X-9 X-9 X-9 X-9 X-99 X-00 R R R R R R R R R9 R0 R R R R C9 C9 SJ R R R R TCK_SWDCLK JTAG_TRST TMS_SWDIO TDI TDO_SWO P.0 P.0 RTC_ALARM RESET_IN RESET_OUT P0.-USB_D+ USB_D- P.-CS P. P.9 P. P.-CS P. P. P.0-DQM P.-DQM P. P. P.-MCICLK P.-MCICMD P.-MCIPWR P.-MCIDAT0 P.-MCIDAT P.-MCIDAT P.-MCIDAT P. P. P.0 P. P. P. P. P. P. P. P.0 P.9 VREF VBAT_IN VA A _A ETH_LED ETH_LED ETH_TXP ETH_TXN ETH_RXP ETH_RXN NAND_FLASH_RDY BA0 BA BA BA BA BA BA9 BA0 BA BA BA ABUF_EN BA BA BA BA BA BA BA BA BA9 BA0 BA BA BA BD0 BD BD BD BD BD BD BD BD BD0 BD9 BD BD BD BD BD BOE BWE BBLS0 BBLS BD BD BD BD9 BD0 BD BD BD BD BD BD BD BD BD9 BD0 BD P.0-RMII_TXD0 P.-RMII_TXD P.-RMII_TXEN P.-RMII_MCD P.-RMII_CRS P. P. P.9 P0.-SDA0 P0.-SCL0 P0. P0. P0. P0. P0. P0. P0. P0. P0. P0.0 P0. P0. P0. P0.9 P0.0 P0. P0. P0.-SSP0_SCK P0.-SSP0_SSEL P0.-SSP0_MISO P0.-SSP0_MOSI P0. P0. P0. P0.9 P0.0 P0. P0.9-USB_D+ P0.0-USB_D- P.0 P. P. P.9 P. P.-TRACEDATA P.-TRACEDATA P.-TRACEDATA0 P.-TRACECLK P. P. P.0 P.-TRACEDATA P. P.-BLS P.9-BLS _EXT P.0-CS0 BBLS BBLS BCS0 BCS P.-CS BCS BCS CARD_DETECT P. P. P. P. P. Expansion Connector (SODIMM Edge Connector) on -bit databus version Former DBUS_EN Normally NC Former BDQM Former BDQM0 Former BCAS Former BRAS Former NC Former NC Former NC Former ETH_PHY_PD - normally shorted Former JTAG_DBGEN Former RTCK